A digital circuit may have multiple blocks. Each block may have multiple digital devices. The digital devices operate according to a respective clock signal. Digital devices are generally clock edge sensitive. A digital device may be made to operate according to a positive edge of a clock signal and/or a negative edge of the clock signal. An edge of the clock signal according to which a digital device is made to operate is referred as an active edge of the clock signal. For the purpose of illustration hereinafter the discussion is presented assuming that all the devices operating according to positive edge of the clock signal.
Further, for the purpose of this discussion, setup time is defined as duration of minimum time before an active edge of the clock signal of a digital device, for which the signal is required to be present at the input of the digital device. Hold time is defined as duration of minimum time for which the signal is required to be present at the input of a digital device after an active edge of the clock signal of a digital device. FIG. 1 shows the hold time and setup time according to respective definitions.
Furthermore, for the purpose of this discussion, a meta-stable state is defined as a state of a digital device when output of the digital device in not valid. For example, an output of the digital device may oscillate or may be at a state which not identified as a valid state of the output. A digital device may come out of the meta-stable state on its own however, when the digital devices comes out of the meta-stable state, the output of the digital device is not known and it can assume any valid digital state that may not be the correct or desired digital state according to the inputs of the digital device.
Within a block the devices may operate according to a first clock signal that has particular characteristics, however digital devices of other blocks may operate according to another clock signal that may have characteristics different than the first clock signal. For communicating a correct and meaningful signal between blocks operating according to clock signals having different characteristics requires synchronizing of the signal. Synchronizing of the signal is critical for ensuring that the signal communicated from a source block to a destination block meets setup time and hold time requirements of the destination block. A communication signal meets these requirement is necessary for a block to ensure that the block or a digital device of the block does not enters into a meta-stable state.
To avoid such situations existing art provides a synchronizer, which ensures that a digital device does not enter into a meta-stable state. FIG. 2 shows a digital circuit 200 having a synchronizer 210. The digital circuit 200 has a source block 220 and a destination block 230. The source block 220 is operating according to a clock signal CLKA and the destination block 230 is operating according to a clock signal CLKB. The source and destination blocks 220 and 230 have flip-flops 222 and 232 respectively. The output of the flip-flop 222 is provided to the input of the flip-flop 232 via the synchronizer 210. The synchronizer 210 is generally a series of cascaded digital devices. Typically these digital devices are flip-flops. The synchronizer 210 operates according to the clock signal CLKB. The number of serially cascaded flip-flops determines the effectiveness of the synchronizer 210 for suppressing the meta-stability of destination block. The operation of the synchronizer 210 can be understood as follows.
The flip-flop 212 receives a communication signal from the source block 220. This communication signal may violate setup and hold time requirement of the flip-flop 212 of the synchronizer 210, which may lead to the flip-flop 212 in a meta-stable state. However since the flip-flop 212 operates according to clock CLKB, it is likely that the output (although a meta-stable output) of the flip-flop 212 will satisfy the setup and hold time requirement of the flip-flop 214 while the output of the flip flop 212 is oscillating or has settled after coming out of meta-stable state. Therefore, the input received by flip-flop 214 is an input that meets the setup and hold time of flip-flop 214 and hence the output of the flip-flop 214 may be a meta-stable free output. As the number of cascaded flip-flop is increased the probability of last flip-flop—that provides input to destination block—of the series being in a meta-stable state decreases. Accordingly likelihood of destination block receiving a signal that would force the digital devices of the destination blocks in a meta-stable state decreases.
The synchronizer 210 described above addresses issue of providing a meta-stable free input for the destination block. However this synchronizer 210 may provide an incorrect input to the destination block. To understand this behavior, consider an example in which a pulse signal of the source block is being synchronized using synchronizer 210. Suppose period of the clock signal CLKB differs from the clock signal CLKA by a small value or the period CLKB is significantly greater than the clock signal CLKA. In such cases as shown in FIG. 3, FIG. 4 and FIG. 5 it may be possible that a single clock cycle pulse can cause setup/hold time violation during two consecutive edges of the destination clock. The pulse might be missed completely in the destination clock domain. However, a pulse can be seen sometimes in the destination clock domain if either the destination flip-flop settles to the correct value after metastability or when the input signal met both the setup time and hold time of the flip-flop by chance.
FIG. 3 shows a timing diagram when, the clock signals CLKA and CLKB are have substantially the same period and are in phase with one another. SigA is the input of the synchronizer 210 and SigB is the output of the synchronizer 210. In this case any violation of step up/hold time at time T1 or T2 would result in an unknown state at SigB which is shown by hash.
FIG. 4 shows a timing diagram when, the clock signals CLKA and CLKB are have substantially the same period and are completely out of phase with one another. In this case a state transition of SigA may get partially registered at time T on SigB because no setup or hold time violation is observed at time T.
FIG. 5 shows a timing diagram when, the clock signal CLKA has a period substantially lower as compared to the clock signal CLKB. In this case a transition at time T1 and time T2 in SigA may completely go unregistered in SigB.